1. Field of the Invention
The present invention relates to a method and apparatus for handling high speed data, and more particularly, to the handling of a continuous stream of high speed data.
2. Description of the Prior Art
Standard memory storage systems utilize bank switching, data latching, or FIFO techniques to read or write data into a read/write memory (RAM). These techniques are adequate for most applications; however, they require too much parallelism in architecture and circuitry overhead to be feasible for high speed applications. A normal memory cycle in a conventional RAM occurs at only 4 MHz. In certain applications, for example, in data acquisition from a high resolution CRT, it is necessary to acquire large amounts of continuous data at speeds greater than 40 MHz.
In U.S. Pat. No. 4,648,077, there is disclosed a serially accessed semiconductor memory which comprises four memory arrays disposed on a single semiconductor chip. A shift register is associated with each of the memory arrays, and transfer gates are disposed between the memory arrays and the shift registers. The patented device is primarily for use as a video memory in which the memory is pixel mapped such that one row of memory elements, or portion thereof, directly corresponds to the pixel information of a given scan line. The information in a row is accessed and stored in a shift register for serial output therefrom during a given scan line. A disadvantage of the disclosed arrangement is that when all of the data has been moved out of the shift registers, there must be a pause while new data is moved into the shift registers. A similar disadvantage exists when data is written into the device; that is, when the four shift registers have been filled, there must be a break in the data stream while the data is moved from the shift registers into memory. Thus, such an arrangement is not suitable for acquiring a continuous stream of data at a rate sufficient, for example, for acquiring data from a high resolution CRT.